Answer in brief
CVE-2024-42279 records a Unknown severity vulnerability in spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer. The current sources do not mark it as known exploited. The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
Analysis pending evidence review
HOL Guard separates source facts from reviewed analysis. See the methodology.
A CVSS score is not reported in the current record. The current sources do not mark it as known exploited. Treat this as a source-backed prioritization signal, not a statement about your environment.
Analysis status
Analysis pending evidence review
Factual feed record only; HOL analysis is not approved for indexing. Read the methodology.
The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
| Package | Affected range | Fixed version |
|---|---|---|
| Linux/Linuxgeneric | >=9ac8d17694b66d54b13e9718b25c14ca36dbebbd <3feda3677e8bbe833c3a62a4091377a08f015b80 || >=9ac8d17694b66d54b13e9718b25c14ca36dbebbd <45e03d35229b680b79dfea1103a1f2f07d0b5d75 || >=9ac8d17694b66d54b13e9718b25c14ca36dbebbd <9cf71eb0faef4bff01df4264841b8465382d7927 | 3feda3677e8bbe833c3a62a4091377a08f015b80, 45e03d35229b680b79dfea1103a1f2f07d0b5d75, 9cf71eb0faef4bff01df4264841b8465382d7927 |
| Linux/Linuxgeneric | 6.0 | Not reported |
Published upstream
Aug 17, 2024
Evidence: source:cvelist:source_dates:source-dates:recordSource modified
Aug 5, 2026
Evidence: source:cvelist:source_dates:source-dates:recordFirst seen by HOL
Aug 5, 2026
In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
Quoted source text, attributed separately from HOL analysis.
Answer in brief
CVE-2024-42279 records a Unknown severity vulnerability in spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer. The current sources do not mark it as known exploited. The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
Analysis pending evidence review
HOL Guard separates source facts from reviewed analysis. See the methodology.
A CVSS score is not reported in the current record. The current sources do not mark it as known exploited. Treat this as a source-backed prioritization signal, not a statement about your environment.
Analysis status
Analysis pending evidence review
Factual feed record only; HOL analysis is not approved for indexing. Read the methodology.
The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
| Package | Affected range | Fixed version |
|---|---|---|
| Linux/Linuxgeneric | >=9ac8d17694b66d54b13e9718b25c14ca36dbebbd <3feda3677e8bbe833c3a62a4091377a08f015b80 || >=9ac8d17694b66d54b13e9718b25c14ca36dbebbd <45e03d35229b680b79dfea1103a1f2f07d0b5d75 || >=9ac8d17694b66d54b13e9718b25c14ca36dbebbd <9cf71eb0faef4bff01df4264841b8465382d7927 | 3feda3677e8bbe833c3a62a4091377a08f015b80, 45e03d35229b680b79dfea1103a1f2f07d0b5d75, 9cf71eb0faef4bff01df4264841b8465382d7927 |
| Linux/Linuxgeneric | 6.0 | Not reported |
Published upstream
Aug 17, 2024
Evidence: source:cvelist:source_dates:source-dates:recordSource modified
Aug 5, 2026
Evidence: source:cvelist:source_dates:source-dates:recordFirst seen by HOL
Aug 5, 2026
In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
Quoted source text, attributed separately from HOL analysis.