Answer in brief
CVE-2025-38252 records a Unknown severity vulnerability in cxl/ras: Fix CPER handler device confusion. The current sources do not mark it as known exploited. The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
Analysis pending evidence review
HOL Guard separates source facts from reviewed analysis. See the methodology.
A CVSS score is not reported in the current record. The current sources do not mark it as known exploited. Treat this as a source-backed prioritization signal, not a statement about your environment.
Analysis status
Analysis pending evidence review
Factual feed record only; HOL analysis is not approved for indexing. Read the methodology.
The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
| Package | Affected range | Fixed version |
|---|---|---|
| Linux/Linuxgeneric | >=36f257e3b0ba904f5a4e7fa8dafaa60e88cdd28c <4bcb8dd36e9e3fad6c22862ac5b6993df838309b || >=36f257e3b0ba904f5a4e7fa8dafaa60e88cdd28c <3c70ec71abdaf4e4fa48cd8fdfbbd864d78235a8 | 4bcb8dd36e9e3fad6c22862ac5b6993df838309b, 3c70ec71abdaf4e4fa48cd8fdfbbd864d78235a8 |
| Linux/Linuxgeneric | 6.15 | Not reported |
Published upstream
Jul 9, 2025
Evidence: source:cvelist:source_dates:source-dates:recordSource modified
Aug 5, 2026
Evidence: source:cvelist:source_dates:source-dates:recordFirst seen by HOL
Aug 5, 2026
In the Linux kernel, the following vulnerability has been resolved: cxl/ras: Fix CPER handler device confusion By inspection, cxl_cper_handle_prot_err() is making a series of fragile assumptions that can lead to crashes: 1/ It assumes that endpoints identified in the record are a CXL-type-3 device, nothing guarantees that. 2/ It assumes that the device is bound to the cxl_pci driver, nothing guarantees that. 3/ Minor, it holds the device lock over the switch-port tracing for no reason as the trace is 100% generated from data in the record. Correct those by checking that the PCIe endpoint parents a cxl_memdev before assuming the format of the driver data, and move the lock to where it is required. Consequently this also makes the implementation ready for CXL accelerators that are not bound to cxl_pci.
Quoted source text, attributed separately from HOL analysis.
Answer in brief
CVE-2025-38252 records a Unknown severity vulnerability in cxl/ras: Fix CPER handler device confusion. The current sources do not mark it as known exploited. The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
Analysis pending evidence review
HOL Guard separates source facts from reviewed analysis. See the methodology.
A CVSS score is not reported in the current record. The current sources do not mark it as known exploited. Treat this as a source-backed prioritization signal, not a statement about your environment.
Analysis status
Analysis pending evidence review
Factual feed record only; HOL analysis is not approved for indexing. Read the methodology.
The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
| Package | Affected range | Fixed version |
|---|---|---|
| Linux/Linuxgeneric | >=36f257e3b0ba904f5a4e7fa8dafaa60e88cdd28c <4bcb8dd36e9e3fad6c22862ac5b6993df838309b || >=36f257e3b0ba904f5a4e7fa8dafaa60e88cdd28c <3c70ec71abdaf4e4fa48cd8fdfbbd864d78235a8 | 4bcb8dd36e9e3fad6c22862ac5b6993df838309b, 3c70ec71abdaf4e4fa48cd8fdfbbd864d78235a8 |
| Linux/Linuxgeneric | 6.15 | Not reported |
Published upstream
Jul 9, 2025
Evidence: source:cvelist:source_dates:source-dates:recordSource modified
Aug 5, 2026
Evidence: source:cvelist:source_dates:source-dates:recordFirst seen by HOL
Aug 5, 2026
In the Linux kernel, the following vulnerability has been resolved: cxl/ras: Fix CPER handler device confusion By inspection, cxl_cper_handle_prot_err() is making a series of fragile assumptions that can lead to crashes: 1/ It assumes that endpoints identified in the record are a CXL-type-3 device, nothing guarantees that. 2/ It assumes that the device is bound to the cxl_pci driver, nothing guarantees that. 3/ Minor, it holds the device lock over the switch-port tracing for no reason as the trace is 100% generated from data in the record. Correct those by checking that the PCIe endpoint parents a cxl_memdev before assuming the format of the driver data, and move the lock to where it is required. Consequently this also makes the implementation ready for CXL accelerators that are not bound to cxl_pci.
Quoted source text, attributed separately from HOL analysis.