Answer in brief
CVE-2026-23361 records a Unknown severity vulnerability in PCI: dwc: ep: Flush MSI-X write before unmapping its ATU entry. The current sources do not mark it as known exploited. The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
Analysis pending evidence review
HOL Guard separates source facts from reviewed analysis. See the methodology.
A CVSS score is not reported in the current record. The current sources do not mark it as known exploited. Treat this as a source-backed prioritization signal, not a statement about your environment.
Analysis status
Analysis pending evidence review
Factual feed record only; HOL analysis is not approved for indexing. Read the methodology.
The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
| Package | Affected range | Fixed version |
|---|---|---|
| Linux/Linuxgeneric | >=beb4641a787df79a1423a8789d185b6b78fcbfea <5e2fc90018635fc982d39f8c11cd3b368fdaf3b7 || >=beb4641a787df79a1423a8789d185b6b78fcbfea <a7afb8f810c04845fdfc58c57d9cf0cc5f23ced0 || >=beb4641a787df79a1423a8789d185b6b78fcbfea <6f60a783860c77b309f7d81003b6a0c73feca49e || >=beb4641a787df79a1423a8789d185b6b78fcbfea <eaa6a56801ddd2d9b4980f19e7fe002b00994804 || >=beb4641a787df79a1423a8789d185b6b78fcbfea <c22533c66ccae10511ad6a7afc34bb26c47577e3 | 5e2fc90018635fc982d39f8c11cd3b368fdaf3b7, a7afb8f810c04845fdfc58c57d9cf0cc5f23ced0, 6f60a783860c77b309f7d81003b6a0c73feca49e, eaa6a56801ddd2d9b4980f19e7fe002b00994804, c22533c66ccae10511ad6a7afc34bb26c47577e3 |
| Linux/Linuxgeneric | 4.19 | Not reported |
Published upstream
Mar 25, 2026
Evidence: source:cvelist:source_dates:source-dates:recordSource modified
Oct 21, 2026
Evidence: source:cvelist:source_dates:source-dates:recordFirst seen by HOL
Oct 21, 2026
In the Linux kernel, the following vulnerability has been resolved: PCI: dwc: ep: Flush MSI-X write before unmapping its ATU entry Endpoint drivers use dw_pcie_ep_raise_msix_irq() to raise an MSI-X interrupt to the host using a writel(), which generates a PCI posted write transaction. There's no completion for posted writes, so the writel() may return before the PCI write completes. dw_pcie_ep_raise_msix_irq() also unmaps the outbound ATU entry used for the PCI write, so the write races with the unmap. If the PCI write loses the race with the ATU unmap, the write may corrupt host memory or cause IOMMU errors, e.g., these when running fio with a larger queue depth against nvmet-pci-epf: arm-smmu-v3 fc900000.iommu: 0x0000010000000010 arm-smmu-v3 fc900000.iommu: 0x0000020000000000 arm-smmu-v3 fc900000.iommu: 0x000000090000f040 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 arm-smmu-v3 fc900000.iommu: event: F_TRANSLATION client: 0000:01:00.0 sid: 0x100 ssid: 0x0 iova: 0x90000f040 ipa: 0x0 arm-smmu-v3 fc900000.iommu: unpriv data write s1 "Input address caused fault" stag: 0x0 Flush the write by performing a readl() of the same address to ensure that the write has reached the destination before the ATU entry is unmapped. The same problem was solved for dw_pcie_ep_raise_msi_irq() in commit 8719c64e76bf ("PCI: dwc: ep: Cache MSI outbound iATU mapping"), but there it was solved by dedicating an outbound iATU only for MSI. We can't do the same for MSI-X because each vector can have a different msg_addr and the msg_addr may be changed while the vector is masked. [bhelgaas: commit log]
Quoted source text, attributed separately from HOL analysis.