Answer in brief
CVE-2026-89916 records a Unknown severity vulnerability in KVM: arm64: Make VNCR invalidation participate in MMU invalidation retry. The current sources do not mark it as known exploited. The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
Analysis pending evidence review
HOL Guard separates source facts from reviewed analysis. See the methodology.
A CVSS score is not reported in the current record. The current sources do not mark it as known exploited. Treat this as a source-backed prioritization signal, not a statement about your environment.
Analysis status
Analysis pending evidence review
Factual feed record only; HOL analysis is not approved for indexing. Read the methodology.
The current feed maps Linux/Linux (generic), Linux/Linux (generic). Check affected ranges and fixed versions before updating.
| Package | Affected range | Fixed version |
|---|---|---|
| Linux/Linuxgeneric | >=4ffa72ad8f37e73bbb6c0baa88557bcb4fd39929 <d8580e7aa189b0c6c5bb4d94b8352728a7c35bbd || >=4ffa72ad8f37e73bbb6c0baa88557bcb4fd39929 <11ee3faab4f1755d126bead9f882e75a7a677860 || >=4ffa72ad8f37e73bbb6c0baa88557bcb4fd39929 <2b7324f3a0c1072b9d578b8d42f199506753f26e | d8580e7aa189b0c6c5bb4d94b8352728a7c35bbd, 11ee3faab4f1755d126bead9f882e75a7a677860, 2b7324f3a0c1072b9d578b8d42f199506753f26e |
| Linux/Linuxgeneric | 6.16 | Not reported |
Published upstream
Sep 16, 2026
Evidence: source:cvelist:source_dates:source-dates:recordSource modified
Sep 16, 2026
Evidence: source:cvelist:source_dates:source-dates:recordFirst seen by HOL
Sep 16, 2026
In the Linux kernel, the following vulnerability has been resolved: KVM: arm64: Make VNCR invalidation participate in MMU invalidation retry A VNCR TLB invalidation can occur on one vcpu while another vcpu is faulting in this same page. Without correctly handling this, we can end up with the following scenario: - vcpu A walks the PTs to translate VNCR - before vcpu A is able to grab the MMU lock to insert the TLB, vcpu B updates the S1 PTs with an invalid entry, and issues a TLBI S1E2 for this VA - vcpu A inserts the TLB for something that is now invalid This isn't a new problem, and we manage S2 by having the MMU notifier to bump up mmu_invalidate_seq on invalidation so that the fault can be replayed. We can perform something similar here, and extend invalidate_vncr_va() to update the same counter, clearly indicating that the context has changed under our feet. This is safe as the invalidation always happen while holding the MMU lock for write, and that we sample the sequence number before walking S1.
Quoted source text, attributed separately from HOL analysis.